reorg of the ECP5 Clock-Reset to be able to add
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 15:48:43 +0000 (16:48 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 16:48:12 +0000 (17:48 +0100)
commit51a16fc59b02e9902ea6d096d921091f1b190a3b
treebf832baa6c5110d805ea37b557706879f209bcd6
parent1b176822349c1f6c828e0156534e2f4d42e1841e
reorg of the ECP5 Clock-Reset to be able to add
a 2nd clock (DRAM)
src/ecp5_crg.py