sort out build of chip/corona using experiments10_verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:05:30 +0000 (19:05 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:05:47 +0000 (19:05 +0100)
commit52084147ba3485128d93334f6fccb38e626ec46d
tree53958f10edf0837438a62f31046a4f3220ad98a2
parent046b6651bf3543b6ae483832e25ea5010dfaf7ee
sort out build of chip/corona using experiments10_verilog
ls180/post_pnr/cocotb/Makefile
ls180/post_pnr/vhd2obj.py