projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ce0b7f1) | patch
add beginnings of syscon bus peripheral
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 13:51:53 +0000 (13:51 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 13:51:53 +0000 (13:51 +0000)
commit554a9ed0ebc833dae1694c6404b6c0d7866b0c91
treeda8a2af9af50c29fa534851509f6748282324266tree
parentce0b7f11bf49ef53362e3e953bd594e762b42ccbcommit | diff
add beginnings of syscon bus peripheral
src/soc/bus/syscon.py [new file with mode: 0644] blob