mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 18 Feb 2019 18:08:14 +0000 (18:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 18 Feb 2019 18:08:14 +0000 (18:08 +0000)
commit59953a0d29ab7ab1dc4e293e51378c21797f5f50
treed41bba0f4bec04b1ce1a660e31a67d7d726f2cbf
parentba5101dcf4cb0b553685a262476dced55b67ea51
mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False
src/add/fmul.py