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(parent: a8e2848) | patch
add dummy/fake/ghost PLL blackbox cell
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 May 2021 17:00:20 +0000 (17:00 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 May 2021 17:00:20 +0000 (17:00 +0000)
commit5a89aa732ccb1c69f525637701043885df147d81
tree7da3add86a03d82d68bbab765e781c96148e1504tree
parenta8e2848b2a68ea284f8f066ca22142a25c698dc6commit | diff
add dummy/fake/ghost PLL blackbox cell
to nsxlib experiments9.  based on the dummy/fake/ghost/symbolic
LibreSOCMem previously created
the cell is completely empty, the only important thing is the *existence*
of the cell and its I/O connections
experiments9/coriolis2/settings.py diff | blob | history
experiments9/pll.py [new file with mode: 0644] blob