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(parent: 611420a) | patch
increase wishbone address width to 29 for xics and gpio
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 15:32:23 +0000 (16:32 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 15:32:23 +0000 (16:32 +0100)
commit63335f2b1916907bddbf0bad02360f6b9a4788d9
tree98da0e47b1ac8f3df59bfbecd9cd20a70db3bfa4tree
parent611420aa9f3bcccae23cbac5bfa40da774db6328commit | diff
increase wishbone address width to 29 for xics and gpio
this may not be exactly correct, have to see how it goes
src/soc/litex/florent/libresoc/core.py diff | blob | history