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(parent: f6e17c7) | patch
Add a HDL test case, where we start at the middle of the VL loop
authorCesar Strauss <cestrauss@gmail.com>
Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)
commit65d9c957717dc63d900c3c24e14cf532a604e490
tree837bddc77d377957c9f96441789d8a41406789batree
parentf6e17c7d8644ef11f3b4f3654abbd032acc5c656commit | diff
Add a HDL test case, where we start at the middle of the VL loop

It is expected to fail, since the HDL is not reentrant at this moment.
src/soc/fu/alu/test/svp64_cases.py diff | blob | history