arg CacheRam read output needs delay by 1 cycle
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)
commit6adca6f1e1932557d9dcca07036b32f1b50e0079
tree0a1c16d9d7ee4cec157685171817afc4ad07fc29
parentfddcd5ff3cbb4580ba734d1e9ad641770e57f8a8
arg CacheRam read output needs delay by 1 cycle
src/soc/experiment/dcache.py