pass state (MSR/PC) around between PowerDecode2, DMI, and TestIssuer
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Aug 2020 19:19:17 +0000 (20:19 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Aug 2020 19:19:17 +0000 (20:19 +0100)
commit6b4a6340086a3e316c1a92266046515880a5efcd
treead392176baa817d882c9459eeb4bb701fb061c54
parent0b7ca0d042438c9760e669499f37c2a292bf3250
pass state (MSR/PC) around between PowerDecode2, DMI, and TestIssuer
src/soc/decoder/power_decoder2.py
src/soc/simple/issuer.py