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(parent: 5b0974d) | patch
attempt to do 8-bit downconvert on wishbone bus for uart,
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 15:43:30 +0000 (15:43 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 15:43:30 +0000 (15:43 +0000)
commit6d88cc5ca3b72929942a6cc3194521ae36b9eaaa
treec5596ef9213e042a939ad20ff09d839f0760a054tree
parent5b0974dcb8dac795b8754de65c510667ad7a20d6commit | diff
attempt to do 8-bit downconvert on wishbone bus for uart,
but it is probably actually 8-bit data aligned to 32-bit
(see soc.vhdl in microwatt)
also set CTS,DSR,RI, DCD to default values
src/ls2.py diff | blob | history