add simple wishbone GPIO peripheral
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 13:27:30 +0000 (14:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 13:27:30 +0000 (14:27 +0100)
commit6dfd19e394790558ed41a2991624bbc331d1150d
tree4ac5298984d640d56657f06b3a6c9696d5ed870b
parent2b32e30a7d4d5b536728bd2594d8b217e1d03efc
add simple wishbone GPIO peripheral
src/soc/bus/simple_gpio.py [new file with mode: 0644]
src/soc/bus/test/wb_rw.py [new file with mode: 0644]
src/soc/fu/shift_rot/test/test_pipe_caller.py