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(parent: b263f3f) | patch
Implement a true 1W/1R memory from 1RW blocks
authorCesar Strauss <cestrauss@gmail.com>
Sat, 9 Apr 2022 21:15:52 +0000 (18:15 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 10 Apr 2022 11:12:29 +0000 (08:12 -0300)
commit6ffbcf1a8dab6eb83042483cec2a5c4c018d46dd
treebec3a7c520db192ce8dedf281f6c4bf81f051749tree
parentb263f3f6f134c2f1d9be78d69b1799b3fbd90b4dcommit | diff
Implement a true 1W/1R memory from 1RW blocks

Uses four phased memories, multiplexers, and FFRAM for the LVT.
Only non-transparent reads, for now.
Test case is included, seems to work.
src/soc/regfile/sram_wrapper.py diff | blob | history