sort out jtag clock/reset interchange
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 30 Jul 2018 10:00:55 +0000 (11:00 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 30 Jul 2018 10:00:55 +0000 (11:00 +0100)
commit711da41d5e3520e617220484b3e9e99ab8298489
tree8505ba895b2dd0f2c07f1b0bcf00fa744381cb97
parent51e418cc9eacea5039c76ad17d9a2ca595c40677
sort out jtag clock/reset interchange
src/bsv/peripheral_gen/base.py
src/bsv/peripheral_gen/jtag.py