fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Jun 2020 10:45:34 +0000 (11:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Jun 2020 10:45:34 +0000 (11:45 +0100)
commit756a92619526c8704d149bb5996509f9cc08ea2d
tree71bf6a8976969672178ba7bab4ff43db0bf52577
parent0155f97fdc2f6a245449c10fafdef91b4ba272ac
fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
src/soc/decoder/power_decoder2.py
src/soc/decoder/power_regspec_map.py
src/soc/regfile/regfiles.py