first cut at Arty A7 Clock-Reset-Generator with S7 PLL
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Mar 2022 11:34:42 +0000 (11:34 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Mar 2022 11:34:42 +0000 (11:34 +0000)
commit7601689cf6f027a5a2866011b2df61bb0bcdac59
tree6ea5ff867704665066c85c532231b0ee46971c39
parent28a6cb43060aff42585ff880755a0237cf235d6a
first cut at Arty A7 Clock-Reset-Generator with S7 PLL
src/arty_crg.py
src/ls2.py