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(parent: 23505ed) | patch
TLB PLRUs are of TLB_WAY_BITS width
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Sep 2020 12:34:15 +0000 (13:34 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Sep 2020 12:34:15 +0000 (13:34 +0100)
commit791602c27729a3f6c20115ee35b55253d43a1224
treea3c987fe1a285ca151f1ab40d247567441a2ea3ctree
parent23505ed4eb98ba9c3bcc500ced0f495cef1613a4commit | diff
TLB PLRUs are of TLB_WAY_BITS width
src/soc/experiment/dcache.py diff | blob | history