projects / riscv-tests.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ea9e37f) | patch
Improve RVC test
authorAndrew Waterman <andrew@sifive.com>
Fri, 4 Aug 2017 07:23:04 +0000 (00:23 -0700)
committerAndrew Waterman <andrew@sifive.com>
Fri, 4 Aug 2017 07:24:37 +0000 (00:24 -0700)
commit7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b
treea812037174bae4e6667edd66ef9be5074b7d1855tree
parentea9e37ff1411a8648710b5539b0971bb5ae9571fcommit | diff
Improve RVC test

Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.
benchmarks/common/test.ld diff | blob | history
env diff | blob | history
isa/rv64uc/rvc.S diff | blob | history