* use readl and writel for accessing memory

* use readl and writel for accessing memory
* add #defines for timer loops to make it possible to shorten
  time taken in simulations when running firmware in verilator
* try pulling DRAM DFII reset HI under software control
* split out DomainRenamer for DRAM Core
* add strange-looking way to expose DFII pads on FakePHY (simulated PH)
  which ensures that, under simulation, a batch of HDL does not get
  deleted: the clk_en, reset and odt parameters deep in the DFII
  interface connected to CSRs are *not* actually connected to anything
  "real" and consequently get deleted... oh and anything connecting
  to them)
* add some firmware debug print statements that need to go some time