uart clock and reset
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 30 Jul 2018 04:47:28 +0000 (05:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 30 Jul 2018 04:47:28 +0000 (05:47 +0100)
commit809f6265ce59b8ec94a2efd6a23b9a4574d444b2
treea9a7a8f4bced89b75d8e5dc524ab4b37320bec1c
parentb269f22ce4cb716b65a3aabcd4c70c062629a730
uart clock and reset
src/bsv/peripheral_gen/quart.py