projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4cb437e) | patch
core hazard bitvector regfiles need to be readable
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 17 Nov 2021 17:42:05 +0000 (17:42 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 17 Nov 2021 18:01:35 +0000 (18:01 +0000)
commit81b013cceefaec4457df0e75a1aab8ab8fb3c30f
tree065626d303643691ec1386caa37aee8a36419f61tree
parent4cb437e3fe727061779eec2bf4a9916fd1ad0a96commit | diff
core hazard bitvector regfiles need to be readable
immediately (combinatorial) not via sync.  allow synced option to
pass through from VirtualRegPort to RegFileArray
src/soc/regfile/regfiles.py diff | blob | history
src/soc/regfile/virtual_port.py diff | blob | history