remove verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 14:59:14 +0000 (14:59 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 14:59:14 +0000 (14:59 +0000)
commit83486d7e84c2f9c97c1567c6524ff9e1890f67de
tree380c1007080b45a40c62d9eb6d5c4ed791744d2c
parent9f0aa878789ad928e8b531fceb6aba606cc72c1a
remove verilog
src/add/nmigen_add_experiment.py