git.libre-soc.org Git - soc.git/commit

author	Jacob Lifshay <programmerjake@gmail.com>
	Mon, 6 Apr 2020 00:12:20 +0000 (17:12 -0700)
committer	Jacob Lifshay <programmerjake@gmail.com>
	Mon, 6 Apr 2020 00:12:20 +0000 (17:12 -0700)
commit	83f98eac357043f8940984eeeaf8d29072c32cb4
tree	13830ef794a06eadcb0cf3c3b5c88ac7efb1bf01	tree
parent	1117d7c3cd52cc73a757f3c6f62c6602551d7ad3	commit \| diff

almost all tests work

40 files changed:

.gitlab-ci.yml		diff \| blob \| history
src/soc/TLB/AddressEncoder.py		diff \| blob \| history
src/soc/TLB/Cam.py		diff \| blob \| history
src/soc/TLB/MemorySet.py		diff \| blob \| history
src/soc/TLB/PermissionValidator.py		diff \| blob \| history
src/soc/TLB/SetAssociativeCache.py		diff \| blob \| history
src/soc/TLB/TLB.py		diff \| blob \| history
src/soc/TLB/ariane/test/test_plru.py		diff \| blob \| history
src/soc/TLB/ariane/test/test_ptw.py		diff \| blob \| history
src/soc/TLB/ariane/test/test_tlb.py		diff \| blob \| history
src/soc/TLB/ariane/test/test_tlb_content.py		diff \| blob \| history
src/soc/TLB/ariane/tlb.py		diff \| blob \| history
src/soc/TLB/ariane/tlb_content.py		diff \| blob \| history
src/soc/TLB/test/test_LFSR2.py		diff \| blob \| history
src/soc/TLB/test/test_address_encoder.py		diff \| blob \| history
src/soc/TLB/test/test_cam.py		diff \| blob \| history
src/soc/TLB/test/test_cam_entry.py		diff \| blob \| history
src/soc/TLB/test/test_permission_validator.py		diff \| blob \| history
src/soc/TLB/test/test_pte_entry.py		diff \| blob \| history
src/soc/TLB/test/test_set_associative_cache.py		diff \| blob \| history
src/soc/TLB/test/test_tlb.py		diff \| blob \| history
src/soc/decoder/isa/.gitignore	[new file with mode: 0644]	blob
src/soc/decoder/isa/test_caller.py		diff \| blob \| history
src/soc/decoder/pseudo/parser.py		diff \| blob \| history
src/soc/experiment/compldst.py		diff \| blob \| history
src/soc/experiment/cscore.py		diff \| blob \| history
src/soc/experiment/score6600.py		diff \| blob \| history
src/soc/iommu/axi_rab/ram_tp_no_change.py		diff \| blob \| history
src/soc/iommu/axi_rab/ram_tp_write_first.py		diff \| blob \| history
src/soc/minerva/core.py		diff \| blob \| history
src/soc/minerva/test/.gitignore	[new file with mode: 0644]	blob
src/soc/minerva/test/test_units_divider.py		diff \| blob \| history
src/soc/minerva/test/test_units_multiplier.py		diff \| blob \| history
src/soc/minerva/units/debug/top.py		diff \| blob \| history
src/soc/minerva/units/multiplier.py		diff \| blob \| history
src/soc/scoreboard/fn_unit.py		diff \| blob \| history
src/soc/scoreboard/ldst_matrix.py		diff \| blob \| history
src/soc/scoreboard/test_mem2_fu_matrix.py		diff \| blob \| history
src/soc/scoreboard/test_mem_fu_matrix.py		diff \| blob \| history
src/soc/simulator/test_sim.py		diff \| blob \| history

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