projects / ls2.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 3d9a298) | patch
add FPGA argument to DDR3SoC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 21:01:11 +0000 (21:01 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 21:01:11 +0000 (21:01 +0000)
commit8796874b70831ccaa7c0f4945b74cdf5fef3db81
tree9af5c3ceaf88a15b44efee86751a3c3a93c71cectree
parent3d9a298748a20dcb3ef5bb6283c0e37b921f4c85commit | diff
add FPGA argument to DDR3SoC
src/ls2.py diff | blob | history