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(parent: 3cd49ba) | patch
re-add CRG (clock reset generator)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 21:11:57 +0000 (22:11 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 21:11:57 +0000 (22:11 +0100)
commit88500487e3a5292b0abd06bef0c118849e40f9a0
tree9209db4475221f6bb3fd8fd1e64eb8711c696263tree
parent3cd49ba3ba82391f6586495fc0e429828bb7c149commit | diff
re-add CRG (clock reset generator)
src/soc/litex/sim.py diff | blob | history