projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0ee5e92) | patch
MTMSR(D) properties.
authorSamuel A. Falvo II <kc5tja@arrl.net>
Sun, 26 Jul 2020 20:31:17 +0000 (13:31 -0700)
committerSamuel A. Falvo II <kc5tja@arrl.net>
Sun, 26 Jul 2020 20:33:07 +0000 (13:33 -0700)
commit8c398d8c100be10b21cc2c193b39a112cc331dc1
treebe9f494d4a986bd7bfce7c0ca2a203f5d248a514tree
parent0ee5e92264b539e4938427c296e8d1477ae704a7commit | diff
MTMSR(D) properties.

As of this commit, the properties for MTMSRD fails because (IBM) bit 30
is not set correctly.  I've double checked my properties against that
specified in the V3.0B specs on page 978.  I've also double-checked the
code in ../main_stage.py.  As of this commit, I *cannot* find the
location of the discrepency.
src/soc/fu/trap/formal/proof_main_stage.py diff | blob | history