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(parent: 8c0a56c) | patch
add hard stop address in ifetch unit test, bit of a mess:
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Dec 2021 21:26:25 +0000 (21:26 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Dec 2021 21:26:25 +0000 (21:26 +0000)
commit8d25dfae6a9f018dc9fc805f495e836c8dee608e
tree3a1610b88bb3518688febd2481c8654b95b9895atree
parent8c0a56c349b0d5650026e0ce9031272104cdc39acommit | diff
add hard stop address in ifetch unit test, bit of a mess:
TestIssuerFSM is just being caught on the edge of attempting to execute
another instruction at a TRAP point
src/soc/simple/issuer.py diff | blob | history
src/soc/simple/test/test_issuer_mmu_ifetch.py diff | blob | history
src/soc/simple/test/test_runner.py diff | blob | history