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(parent: 205b545) | patch
LDSTException now passing bits of SRR1 around to the Trap Pipeline
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 Jan 2022 00:42:44 +0000 (00:42 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 Jan 2022 00:42:44 +0000 (00:42 +0000)
commit90c5d19398f6f28272f320e078b94afa965f58a3
tree632ed96370b0e7372f3420ee633d998b3ac216aetree
parent205b54594eb4a8614c44fe0ddf7a8e59d7076da5commit | diff
LDSTException now passing bits of SRR1 around to the Trap Pipeline
the actual (former) value of SRR1 is not what is supposed to be used:
the use of the variable "srr1" is a moniker from microwatt
src/soc/fu/ldst/loadstore.py diff | blob | history
src/soc/fu/trap/main_stage.py diff | blob | history
src/soc/fu/trap/trap_input_record.py diff | blob | history