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(parent: 7feec03) | patch
move cia and msr to trap input record
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 21 Jul 2020 14:25:27 +0000 (15:25 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 21 Jul 2020 14:25:27 +0000 (15:25 +0100)
commit930dd76d7472508ae57188bd0ef354ad5a039ff8
treeff353b39b4f1cc608e30df7637b45495bfc0e0cbtree
parent7feec03ab04179912d812ed0e18d4144fd7ce8b5commit | diff
move cia and msr to trap input record
src/soc/fu/compunits/test/test_compunit.py diff | blob | history
src/soc/fu/test/common.py diff | blob | history
src/soc/fu/trap/main_stage.py diff | blob | history
src/soc/fu/trap/pipe_data.py diff | blob | history
src/soc/fu/trap/test/test_pipe_caller.py diff | blob | history
src/soc/fu/trap/trap_input_record.py diff | blob | history