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(parent: c030176) | patch
add misaligned mmu.bin test 5 notes: currently LoadStore1 does not
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 28 Dec 2021 02:30:11 +0000 (02:30 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 28 Dec 2021 02:30:11 +0000 (02:30 +0000)
commit93a94cddab5483f840d0d2029d660e5655983c5f
tree35a7934cbbd9845baf1421b81344cbd426c1235atree
parentc030176faf54e1941c75fc6a4bfb6ecc6a280440commit | diff
add misaligned mmu.bin test 5 notes: currently LoadStore1 does not
support misaligned LD/ST therefore a 0x600 exception is raised
where actually a page-table lookup over the boundary (into a second
PTE which does not exist) should result in a 0x300 (DAR) fault.

also took the opportunity to set align_intr when no-cache is requested
on dcbz
src/soc/experiment/mmu.py diff | blob | history
src/soc/fu/ldst/loadstore.py diff | blob | history