add option to generate verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Jul 2020 14:04:43 +0000 (15:04 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 18 Jul 2020 22:17:51 +0000 (23:17 +0100)
commit95eed9f8c85aaca0f913abb6f752391f92d5ec84
tree96f719e2060a847fafbca244c7b14fc5608e2aa4
parent85970bb28b1b3ba1b0d82641d281be5566de687d
add option to generate verilog
src/soc/simple/issuer.py