sort out MSR, read/write in same way as PC/SVSTATE in TestIssuer
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 15 Dec 2021 12:59:48 +0000 (12:59 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 15 Dec 2021 12:59:48 +0000 (12:59 +0000)
commit96066b54a9f95973223ae361cebdcea10e12f955
treec03412fd64e94b2608901fdeda1433bbfa5a8ec5
parent29b0c7a5f3cf92b3140f5023952cc1d9abaa52a3
sort out MSR, read/write in same way as PC/SVSTATE in TestIssuer
src/soc/simple/core_data.py
src/soc/simple/issuer.py