add SDRAM clock output
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Aug 2018 06:35:56 +0000 (07:35 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Aug 2018 06:35:56 +0000 (07:35 +0100)
commit9a8190f066f0d66cfb39ded12493ad1a3c15b0b1
tree68497c75313cd7186ed3c8b8b2878dcb1d95fb21
parenta1b5d99a7317ad6b777699238881d9c976cf2b6c
add SDRAM clock output
src/bsv/peripheral_gen/sdram.py
src/spec/pinfunctions.py