sort out platform IO pads for iverilog hyperram sim
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 26 Mar 2022 21:21:48 +0000 (21:21 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 26 Mar 2022 21:21:48 +0000 (21:21 +0000)
commit9bd0292a92ca7f1af25627778dd38c6cf90f91e1
treeae382e1d0880c0978ba0eed666819fc98fa86edb
parent6233c37eb67bb6f4350d661d4df8c13a004cbc05
sort out platform IO pads for iverilog hyperram sim
runsimsoc_hyperram.sh
src/ls2.py