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(parent: a9e76d8) | patch
add stall signal to arbiter, assume nmigen-soc takes
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 9 Mar 2022 12:12:51 +0000 (12:12 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 9 Mar 2022 12:12:51 +0000 (12:12 +0000)
commit9d278400b01d75fbb4cae435292f632dd6292016
tree94045082c077d66ee111d5f0f90e98cf936ffe3etree
parenta9e76d84c643cef88584e33ef9978642cdd23ce6commit | diff
add stall signal to arbiter, assume nmigen-soc takes
care of adaptation from WB4-pipeline-burst to WB3-classic
src/ls2.py diff | blob | history