FSGNJ working now in all three modes

FSGNJ working now in all three modes

This adds the functionality of the FSIGNJ RISCV instruction, namely:

When the opcode is 0x00 - it combines the sign bit of operand B with
the rest of the value in operand A
When the opcode is 0x01 - it combines the inverted sign bit of operand
B with the rest of the value in operand A
When the opcode is 0x02 - it combines the sign bit composed of the
exclusive OR of the sign bits of A and B with the rest of the value in
operand A

This also modifies the unit test for the module to test each of these
behaviors for 32 bit floats