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(parent: 955f5d4) | patch
set clock freq Constant length to 32-bit in Tercel.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 18:18:07 +0000 (19:18 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 18:18:07 +0000 (19:18 +0100)
commit9e4e5fb690bf8a893c17f5f02ffbb6728f720eb8
tree3da2e69db2eee5f0b0b1186cb91ee47e95c70eb3tree
parent955f5d408051d75f20355b6c5f4fb98d64d8c263commit | diff
set clock freq Constant length to 32-bit in Tercel.
this really needs to come from SYSCON
src/soc/bus/tercel.py diff | blob | history