add misalign flag to PortInterfaceBase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 9 May 2021 12:29:19 +0000 (13:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 9 May 2021 12:29:19 +0000 (13:29 +0100)
commita11db6bdea5c50a7afc424855e57797a4353b063
tree8223c0ac24a2ed1c23ef6854fd8d9f3e77b815ba
parente7df7e09c4e5cafa068e9028e4b245d9e60aed2f
add misalign flag to PortInterfaceBase
allows first exception to be generated
src/soc/experiment/pi2ls.py
src/soc/experiment/pimem.py
src/soc/experiment/test/test_l0_cache_buffer2.py
src/soc/experiment/test/test_mmu_dcache_pi.py
src/soc/fu/ldst/loadstore.py