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(parent: 9ba83df) | patch
not for any good reason, separate adding the uart16550 verilog source
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 13 Feb 2022 14:25:44 +0000 (14:25 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 13 Feb 2022 14:25:44 +0000 (14:25 +0000)
commita3c4783b2fc5a4ea5d22e1932a5e55da8f846d35
treeaf5bd31b99222b6400831e85e434fec9d04e13d2tree
parent9ba83df4c6fa64600337bfe8af9ad4c5fba5785ccommit | diff
not for any good reason, separate adding the uart16550 verilog source
examples/ls2.py diff | blob | history