wishbone bus convert on dcache
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 5 Dec 2021 01:29:58 +0000 (01:29 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 5 Dec 2021 01:29:58 +0000 (01:29 +0000)
commita450dfd9a882008287aa17691f916d6eb247afbc
treed5c498fc408e6d0f2d47369f9e166a253463f4cb
parentb1646c08318bf80fa08eb2651fff6773ea84e018
wishbone bus convert on dcache
src/soc/experiment/dcache.py
src/soc/experiment/test/test_dcache.py
src/soc/experiment/test/test_dcache_tlb.py
src/soc/experiment/test/test_dcbz_pi.py
src/soc/experiment/test/test_ldst_pi.py
src/soc/experiment/test/test_ldst_pi_misalign.py
src/soc/experiment/test/test_loadstore1.py
src/soc/experiment/test/test_mmu_dcache.py
src/soc/experiment/test/test_mmu_dcache_pi.py
src/soc/fu/ldst/loadstore.py
src/soc/fu/mmu/fsm.py