add verilog conversion (commented out)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 15:13:13 +0000 (15:13 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 15:13:13 +0000 (15:13 +0000)
commita710a0d7956529e200ec9198314ef71ca1522b12
tree8857c721f470a0cffb2e1dfa4956a9ac9c9ec60a
parent30392515cf6c026ffaeb6f00f4bc8773d354cbc8
add verilog conversion (commented out)
src/add/nmigen_add_experiment.py