add assertion checking bus write against memory write port granularity
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 12:25:57 +0000 (13:25 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 12:25:57 +0000 (13:25 +0100)
commita79def076ad4979cefc2047b8001a8a12df0ea64
tree5f2fb9b89b3ed64d22d2b5627fbb05168bd600be
parentb061dc21b353a4ae0a4574e744a6b20cfa1926f5
add assertion checking bus write against memory write port granularity
nmigen_soc/wishbone/sram.py