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(parent: c24e13b) | patch
add dummy pll to experiments10_verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:04:27 +0000 (11:04 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:04:27 +0000 (11:04 +0000)
commita876c5dd61a53230de74b2ca2900e0e09490da95
tree4eae900fe4ae310905a4531c749537da5c346d3btree
parentc24e13b1078fa2d358d6b7f91cfd96905c100769commit | diff
add dummy pll to experiments10_verilog
experiments10_verilog/Makefile diff | blob | history
experiments10_verilog/add.py diff | blob | history
experiments10_verilog/doDesign.py diff | blob | history