testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Aug 2020 21:05:12 +0000 (22:05 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Aug 2020 21:05:17 +0000 (22:05 +0100)
commitabf60c9c057e7ec8005f864a16466d9b8ed56f51
tree1958255ceacaef1ccc6682a42c3a5564bd0fd18f
parent1e651d83571fc0dee9f454188d4d34b3c708789e
testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
src/soc/litex/florent/sim.py
src/soc/simple/issuer_verilog.py