projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c9273e2) | patch
create dummy PLL block, connect up to core and clock-selector
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 13:28:54 +0000 (14:28 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 13:28:58 +0000 (14:28 +0100)
commitaecfa299982a14b62a36d809030f7d4a73c6ddff
tree68f442085431c2b93b239ada340b0d19063a986dtree
parentc9273e2cba757e985196df5e57e305ceae858f06commit | diff
create dummy PLL block, connect up to core and clock-selector
src/soc/clock/select.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history
src/soc/simple/test/test_issuer.py diff | blob | history