projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1ed0782) | patch
use a virtual regfile port for the hazard bitvectors
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Nov 2021 18:54:21 +0000 (18:54 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Nov 2021 18:54:26 +0000 (18:54 +0000)
commitb0331bbe19decb29e2adc2ea26082755e3eeb188
tree6fb51f7bf4c56fd88c470872bfa26b9c13d3f7cbtree
parent1ed0782f7a5fb53d0a162ebe1fe337b5a18c9293commit | diff
use a virtual regfile port for the hazard bitvectors
this allows a full width of enables and full width of bits
(one per reg being written to)
src/soc/regfile/regfiles.py diff | blob | history
src/soc/regfile/virtual_port.py diff | blob | history
src/soc/simple/core.py diff | blob | history