projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c354335) | patch
sigh have to allow external clocks and reset mess even in microwatt-compat
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Jan 2022 22:33:39 +0000 (22:33 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Jan 2022 22:33:39 +0000 (22:33 +0000)
commitb35595829fb7e2390a28186008ab9df35131ea8e
tree1d2c96dde553daafe033574a31a20e659b6ced17tree
parentc35433591d902d6f487b7d9a298925e2475c96dbcommit | diff
sigh have to allow external clocks and reset mess even in microwatt-compat
mode.  soc.vhdl still needs to be able to pull an external reset OR
DMI needs to be able to instruct the core to do it. hardly surprising
src/soc/simple/issuer.py diff | blob | history
src/soc/simple/issuer_verilog.py diff | blob | history