checking simulation of Async DDR3
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 17:32:56 +0000 (18:32 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 15 Apr 2022 17:32:56 +0000 (18:32 +0100)
commitb3c1449e498574e7637e1ff7fcae9f6f85132fab
tree7a5c65cda49e1d2cf20b81b6e51ff1c37df18816
parent2b9b7be75a2b405456fedace894a47bc32ed2b14
checking simulation of Async DDR3
simsoc.ys
src/ecp5_crg.py
src/ls2.py