connect up WB SRAM to dcache test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 11 Sep 2020 16:54:50 +0000 (17:54 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 11 Sep 2020 16:54:50 +0000 (17:54 +0100)
commitb4b4589f0328fee2cdcce83710968afded8d33df
tree5bda18648f7457dcd7ddf6dbb540b4d664c284df
parente7ede04747d3b8701b35bb7cf9f9e71eb2652e55
connect up WB SRAM to dcache test
src/soc/experiment/dcache.py
src/soc/experiment/mem_types.py