rename ref to ref_v in PLL due to ref being a verilog keyword
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Jun 2021 14:42:32 +0000 (15:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Jun 2021 14:42:32 +0000 (15:42 +0100)
commitb580c7703fb09fff550ba13c56368ed9b3d097e0
tree4a3344d5b7ad03bf4c918dc8fc786a0eb63f3d4b
parent8ff926f489b50da22fcd00c53bbde79f1659c52d
rename ref to ref_v in PLL due to ref being a verilog keyword
src/soc/clock/dummypll.py