try SDRAM SDR
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 21:42:29 +0000 (22:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 21:44:34 +0000 (22:44 +0100)
commitb72b1ff6810cbcf617217b2fa5095d4a6b92bd69
treea5c95d95794bea39baa2a5d40555a2092bff4955
parent6a16c3d153da91a658bc70b9a1af0bbd52e982c6
try SDRAM SDR
src/soc/litex/sim.py